DIE LEVEL FAULT ISOLATION: Creative approaches for thermal hot spot identification on analog IC
DIE LEVEL FAULT ISOLATION: Creative approaches for thermal hot spot identification on analog IC
Wednesday, November 3, 2021
West Hall 1-2 (Phoenix Convention Center)
Summary:
With the increase in the complexity of semiconductor wafer fabrication processes, the timing in responding and discovering the failure mechanism to a product failure at the initial product development stage or at the end of production line becomes a crucial factor. Effectively utilization the fault localization technique such as Photon Emission Microscopy (PEM), Laser Signal Injection Microscopy (LSIM) and Thermal Hotspot Localization (THS) may be significantly shortened the cycle time in the fault localization process. This paper will illustrates the creative approaches for thermal hot spot identification using modulated THS technique coupled with modified external electrical connection.
With the increase in the complexity of semiconductor wafer fabrication processes, the timing in responding and discovering the failure mechanism to a product failure at the initial product development stage or at the end of production line becomes a crucial factor. Effectively utilization the fault localization technique such as Photon Emission Microscopy (PEM), Laser Signal Injection Microscopy (LSIM) and Thermal Hotspot Localization (THS) may be significantly shortened the cycle time in the fault localization process. This paper will illustrates the creative approaches for thermal hot spot identification using modulated THS technique coupled with modified external electrical connection.