Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method

Monday, November 1, 2021: 3:00 PM

105 AB (Phoenix Convention Center)

Mr. Daniel Nuez , Xilinx, San Jose, CA

Mr. Phoumra Tan , Xilinx, Inc, San Jose, CA

Mrs. Daisy Lu , Xilinx, San Jose, CA

Mr. Benhai Zhang , Xilinx, San Jose, CA

Mr. Tom Harper , Varioscale, San Marcos, CA

Mr. Josh Miller , Varioscale, San Marcos, CA

Mr. Mark Lynaugh , Varioscale, San Marcos, CA

Dr. Michael DiBattista , Varioscale, San Marcos, CA

Mr. Scott Silverman , Varioscale, San Marcos, CA