Die Level Fault Isolation

Monday, November 1, 2021: 3:00 PM-4:15 PM

105 AB (Phoenix Convention Center)

* LVP and LVI

* Static and dynamic emission microscopy

* Static and dynamic laser stimulation

* Thermal Lock-in Thermography

Mr. Dan Bodoh, NXP Semiconductors and Ms. Lesly Endrinal, Qualcomm Technologies Inc.

3:00 PM

Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method
Mr. Daniel Nuez, Xilinx; Mr. Phoumra Tan, Xilinx, Inc; Mrs. Daisy Lu, Xilinx; Mr. Benhai Zhang, Xilinx; Mr. Tom Harper, Varioscale; Mr. Josh Miller, Varioscale; Mr. Mark Lynaugh, Varioscale; Dr. Michael DiBattista, Varioscale; Mr. Scott Silverman, Varioscale

3:25 PM

3:50 PM

(V) Pushing Failure Mode Stimulus to Overcome the Limitation/Boundaries of Soft Defect Localization Tools
Mr. Allan Norico, ON Semiconductor; Mr. Rommel Estores, ON Semiconductor

See more of: Technical Program