Impacts of Substrate Thinning on FPGA Performance and Reliability
Impacts of Substrate Thinning on FPGA Performance and Reliability
Wednesday, November 3, 2021: 9:15 AM
105 AB (Phoenix Convention Center)
Summary:
Global thinning of integrated circuits is a technique that enables backside failure analysis and radiation testing. Prior work also shows increased thresholds for single-event latchup and upset in thinned devices. We present impacts of global thinning on device performance and reliability of 28 nm node field programmable gate arrays (FPGA). Devices are thinned to values of 50, 10, and 3 microns using a micromachining and polishing method. Lattice damage, in the form of dislocations, extend about 1 micron below the machined surface. The damage layer is removed after polishing with colloidal SiO2 slurry. We create a 2D finite-element model with liner elasticity equations and flip-chip packaged device geometry to show that thinning increases compressive global stress in the Si, while C4 bumps increase stress locally. Measurements of stress using Raman spectroscopy qualitatively agree with our stress model but also reveal the need for more complex structural models to account for nonlinear effects occurring in devices thinned to 3 microns and after temperature cycling to 125 degrees C. Thermal imaging shows that increased local heating occurs with increased thinning but the maximum temperature difference across the 3-micron die is less than 2 degrees C. Ring oscillators (ROs) programmed throughout the FPGA fabric slow about 0.5% after thinning compared to full thickness values. Temperature cycling the devices to 125 degrees C further decreases RO frequency about 0.5%, which we attribute to stress changes in the Si.
Global thinning of integrated circuits is a technique that enables backside failure analysis and radiation testing. Prior work also shows increased thresholds for single-event latchup and upset in thinned devices. We present impacts of global thinning on device performance and reliability of 28 nm node field programmable gate arrays (FPGA). Devices are thinned to values of 50, 10, and 3 microns using a micromachining and polishing method. Lattice damage, in the form of dislocations, extend about 1 micron below the machined surface. The damage layer is removed after polishing with colloidal SiO2 slurry. We create a 2D finite-element model with liner elasticity equations and flip-chip packaged device geometry to show that thinning increases compressive global stress in the Si, while C4 bumps increase stress locally. Measurements of stress using Raman spectroscopy qualitatively agree with our stress model but also reveal the need for more complex structural models to account for nonlinear effects occurring in devices thinned to 3 microns and after temperature cycling to 125 degrees C. Thermal imaging shows that increased local heating occurs with increased thinning but the maximum temperature difference across the 3-micron die is less than 2 degrees C. Ring oscillators (ROs) programmed throughout the FPGA fabric slow about 0.5% after thinning compared to full thickness values. Temperature cycling the devices to 125 degrees C further decreases RO frequency about 0.5%, which we attribute to stress changes in the Si.