Sample Preparation and Device Deprocessing

Wednesday, November 3, 2021: 8:00 AM-10:05 AM
105 AB (Phoenix Convention Center)
* Package opening and device deprocessing
* Chemical etching methods
* Mechnanical polishing and laser preparation
Dr. Chuan Zhang, NVIDIA Corporation and Dr. Erwin Hendarto, Silicon Labs
8:00 AM
(V) Large area semiconductor device delayering for failure identification and analyses
Dr. Pawel Nowakowski, E.A. Fischione Instruments, Inc.; Dr. Cecile S. Bonifacio, E.A. Fischione Instruments, Inc.; Ms. Mary Ray, E.A. Fischione Instruments, Inc.; Mr. Paul Fischione, E.A. Fischione Instruments, Inc.
8:25 AM
(V) Selective dry etch removal of Si and SiOxNy for advanced electron beam probing applications
Dr. Mary Edmonds, Intel Corporation; Thaddeus Cox, Intel Corporation; John Markulin, Intel Corporation; Dr. Martin Von Haartman, Intel Corporation
8:50 AM
Dielectric film thickness measurement via a convolutional neural network for integrated circuit delayering end pointing
Mr. Jonathan Scholl, Battelle Memorial Institute; Mr. Nick Darby, Battelle Memorial Institute; Mr. Joshua G. Baur, Battelle Memorial Institute; Mr. Yash Patel, Battelle Memorial Institute; Mrs. Isabel Boona, Battelle Memorial Institute; Dr. Kurtis Wickey, Battelle Memorial Institute; Dr. Jeremiah P. Schley, Battelle Memorial Institute
9:15 AM
Impacts of Substrate Thinning on FPGA Performance and Reliability
Dr. Darin Leonhardt, Sandia National Laboratories; Dr. Thomas Beechem, Sandia National Laboratories; Mr. Matthew Cannon, Sandia National Laboratories; Dr. Nathaniel Dodds, Sandia National Laboratories; Dr. Matthew Fellows, Sandia National Laboratories; Dr. Thomas Grzybowski, Sandia National Laboratories; Dr. Gad Haase, Sandia National Laboratories; Mr. Thomas LeBoeuf, Sandia National Laboratories; Dr. David Lee, Sandia National Laboratories; Dr. William Rice, Sandia National Laboratories
9:40 AM
(V) A Novel Sample Preparation Method for Frontside Inspection of GaN devices after Backside Analysis
Mr. Tony Colpaert, ON SEMICONDUCTOR; Mr. Stefaan Verleye, ON Semiconductor
See more of: Technical Program
<< Previous Session | Next Session >>