Package and Physical Analysis Challenges I

Sunday, October 31, 2021: 8:00 AM-11:50 AM
103 AB (Phoenix Convention Center)
Dr. Wentao Qin, ON Semiconductor and Mr. John Bescup, Jet Propulsion Laboratory
8:00 AM
Chip Scale Packaging and Its Failure Analysis Challenges
Ms. Susan Li, Cypress Semiconductor, An Infineon Technologies Company
9:00 AM
(V) Electromigration Analysis located between the internal layers of a Printed Circuit Board
Dr. Miguel Angel Neri, Doctorate on Materials Engineering, Advanced materiales Research Center, S. C.
10:00 AM
Morning Refreshment Break
10:20 AM
(V) Package Level Fault Isolation
Dr. Lihong Cao, ASE US Inc
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