Avalon-Aided Mapping of Fault Localized Area of ADIs Radar Receive Path Analog FrontEnd Amplifier with 0.18um 6-metal CMOS Fab Process
Avalon-Aided Mapping of Fault Localized Area of ADIs Radar Receive Path Analog FrontEnd Amplifier with 0.18um 6-metal CMOS Fab Process
Tuesday, November 14, 2023: 1:10 PM
104 A-B (Phoenix Convention Center)
Summary:
Analog Devices Inc. (ADI)’s Radar Receive Path Analog Front End Amplifier (AFE) with 0.18um 6-metal Fab Process has failures related to Power-Down and Scan test parameters which were endorsed for Failure Analysis. Fault localization is quite challenging because it involves 6 metal layers. This has been resolved with the availability of Synopsis Avalon software with capability to convert the complete Cadence schematics and layout that is usable for Failure Analysis, through cross-mapping with the fault localized area-of-interest (AOI) on the actual reject part with the die schematics and layout, and identifying the failing component and circuit block. This led to the creation of the failure model related to the reported failure mode and the determination of the appropriate failure mechanism related to fabrication defects between the adjacent metallization layers and defect on between the polysilicon and substrate layer. This helps speed up the FA Cycle Time and achieve an accurate failure mechanism, which later resolved the fab defect issue with the Fab process owner.
Analog Devices Inc. (ADI)’s Radar Receive Path Analog Front End Amplifier (AFE) with 0.18um 6-metal Fab Process has failures related to Power-Down and Scan test parameters which were endorsed for Failure Analysis. Fault localization is quite challenging because it involves 6 metal layers. This has been resolved with the availability of Synopsis Avalon software with capability to convert the complete Cadence schematics and layout that is usable for Failure Analysis, through cross-mapping with the fault localized area-of-interest (AOI) on the actual reject part with the die schematics and layout, and identifying the failing component and circuit block. This led to the creation of the failure model related to the reported failure mode and the determination of the appropriate failure mechanism related to fabrication defects between the adjacent metallization layers and defect on between the polysilicon and substrate layer. This helps speed up the FA Cycle Time and achieve an accurate failure mechanism, which later resolved the fab defect issue with the Fab process owner.