Nanoprobing EBIC Analysis to Locate Silicon Defects in CMOS Devices on SOI Wafers

Summary:

With the increasing complexity of CMOS devices, particularly those fabricated on Silicon-On-Insulator (SOI) wafers, traditional failure analysis techniques such as Wright etch have become challenging. This paper presents the novel application of Electron Beam Induced Current (EBIC) analysis for locating silicon defects in CMOS devices on SOI wafers. The effectiveness of this technique is demonstrated through two case studies. The first involves the identification of a silicon defect in an SOI wafer using EBIC, which is otherwise difficult to reveal through conventional sample preparation methods. The second case study highlights the robustness of this technique by locating silicon pitting in a large-structure CMOS PMOS device. This work represents the first successful application of EBIC for this purpose, underscoring its potential for widespread adoption in the semiconductor industry.