Novel Die Edge Delayering Methodology with Early Defined Lap Stop at Non-Low K Dielectric Layer and Gas Assisted PFIB Delayering

Thursday, November 20, 2025: 1:10 PM
2 (Pasadena Convention Center)
Mr. Benjamin Yuen Sum Lo , NXP Semiconductor, Kaohsiung City, Taiwan
Mr. Andy Hsu , NXP Semiconductor, Kaohsiung City, Taiwan
Mr. Tianyu Yang , NXP Semiconductor, Tianjin, China
Ms. Xinyu Tao , NXP Semiconductor, Tianjin, China
Mr. Rik Otte , NXP Semiconductor, Nijmegen, Netherlands

Summary:

Parallel lapping and Xenon Plasma-Focused Ion Beam (Xe⁺ PFIB) are essential for die-level delayering in advanced nodes. However, delayering near the die edge remains challenging. Traditional planar lapping often causes die corner rounding, leading to sloped surfaces that compromise further analysis accuracy and risk damaging the area of interest (AOI), especially when it's near the die edge. To address this, a novel methodology combines conventional lapping with a mixed-mode PFIB process. The lapping stop layer is redefined at a thicker non-low-k (NLK) dielectric and metal layer, preserving more of the stack and reducing edge rounding. PFIB is then used iteratively on the thick NLK layers with cycles of delayering gas, tungsten (W) deposition, and oxide etching, allowing precise control and uniformity. Once the ultra-low-k (ULK) region is reached, standard PFIB gas exposes deeper metal layers. Case studies on 12-layer metallization stacks show improved AOI flatness and process consistency. This approach enables controlled, repeatable delayering, especially within 20 µm of the die edge, and can be adapted for problematic areas across the die, enhancing reliable in failure analysis of advanced semiconductor devices.