Latency of via failure from corrosion
Latency of via failure from corrosion
Tuesday, November 18, 2025: 12:50 PM
3 (Pasadena Convention Center)
Summary:
The integrity of via structures in semiconductor interconnects is critical to device reliability. A latent increase in via resistance, particularly due to corrosion, can lead to circuit failure long after initial testing. This study investigates the mechanisms behind such delayed failures, focusing on a returned unit exhibiting a phase-locked loop (PLL) lock failure attributed to increased via resistance. Through photoemission analysis and cross-sectional TEM imaging, the failure was traced to corrosion at both the top and bottom of a misaligned via. The misalignment introduced geometric complexity that enabled moisture entrapment, and promoted crevice and galvanic corrosion. This corrosion evolved progressively over time, leading to gradual interfacial resistance increase. The findings highlight the importance of understanding corrosion kinetics, material electrochemical compatibility, and geometric alignment in preventing latent interconnect failures. Mitigation strategies are proposed to enhance long-term device reliability.
The integrity of via structures in semiconductor interconnects is critical to device reliability. A latent increase in via resistance, particularly due to corrosion, can lead to circuit failure long after initial testing. This study investigates the mechanisms behind such delayed failures, focusing on a returned unit exhibiting a phase-locked loop (PLL) lock failure attributed to increased via resistance. Through photoemission analysis and cross-sectional TEM imaging, the failure was traced to corrosion at both the top and bottom of a misaligned via. The misalignment introduced geometric complexity that enabled moisture entrapment, and promoted crevice and galvanic corrosion. This corrosion evolved progressively over time, leading to gradual interfacial resistance increase. The findings highlight the importance of understanding corrosion kinetics, material electrochemical compatibility, and geometric alignment in preventing latent interconnect failures. Mitigation strategies are proposed to enhance long-term device reliability.