Accelerating Time to Market with Unified Scan Diagnostics and Volume-Based Defect Detection

Monday, November 17, 2025: 4:40 PM
3 (Pasadena Convention Center)
Mr. Kiran (Sunny) Thota , NXP, Austin, TX
Mr. Ramesh Saidapet , NXP, Austin, TX
Mr. Dan Bodoh , NXP Semiconductors, Austin, TX
Mrs. Yi Sun , NXP, Austin, TX
Mr. Brandon Ussery , NXP, Austin, TX
Mr. Naren Ramesh , Mentor,a Siemens business, Wilsonville, OR

Summary:

Advanced chips, built on cutting-edge process nodes, are more susceptible to defects during manufacturing, making early detection acritical. This necessity has driven the demand for extensive structural scan testing for screening defects in digital logic of SoC’s to diagnose potential issues early on. Running scan diagnostics to identify structural defects at a high volume is essential for ensuring rapid yield improvement. By incorporating volume-based statistical analysis, manufacturers can dramatically enhance product quality, reduce time to market, and lower customer return rates by minimizing defective parts per million (DPPM). In this paper, we introduce our proprietary production solution: the Unified Scan Diagnostics (USD) Flow. This flow leverages Siemens’ Tessent Diagnosis and Yield Insight engines to perform high-volume scan diagnostics, effectively analyzing test data from various sources. Our automated statistical models analyze defect "callouts," identifying structural issues in silicon and wafers with precision. This flow enables direct Physical Failure Analysis (PFA) and accelerates time to market, shortening production cycles and significantly reducing costs. Process-node agnostic, the USD Flow has been successfully implemented across multiple process nodes, including the most advanced technologies, saving significant time and costs related to non-recurring engineering (NRE) and average unit cost (AUC).