Product Yield, Test and Diagnostics

Monday, November 17, 2025: 4:00 PM-5:00 PM
3 (Pasadena Convention Center)
Jayant D'Souza, SIEMENS USA and Dr. Venkat Ravikumar, Advanced Micro Devices - Singapore Pte Ltd
4:00 PM
Region-based Characterization of Defective Logic Circuits
Ruben Purdy, Carnegie Mellon University; Ziyad Alswaidan, Carnegie Mellon University; Xu He, Carnegie Mellon University; Chris Nigh, Carnegie Mellon University; Shawn Blanton, Carnegie Mellon University
4:20 PM
Accelerated Prediction and Spatial Profiling of HEIP Degradation for Layout-Driven Reliability Analysis
Ms. Gyulyeong Nor, Samsung Electronics; Mr. Jongwon Nam, Samsung Electronics; Mr. Yumin Kim, Samsung Electronics; Mr. Ilwoo Jung, Samsung Electronics; Mr. Dongin Lee, Samsung Electronics
4:40 PM
Accelerating Time to Market with Unified Scan Diagnostics and Volume-Based Defect Detection
Mr. Kiran (Sunny) Thota, NXP; Mr. Ramesh Saidapet, NXP; Mr. Dan Bodoh, NXP Semiconductors; Mrs. Yi Sun, NXP; Mr. Brandon Ussery, NXP; Mr. Naren Ramesh, Mentor,a Siemens business
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