Comprehensive Fault Isolation Technologies for the Gate-All-Around Transistor and Backside Power Delivery Paradigm Shifts

Tuesday, November 18, 2025: 1:10 PM
3 (Pasadena Convention Center)
Mitchell J. Senger , Intel Corporation, Hillsboro, OR
Mauricio Posada , Intel Corporation, Hillsboro, OR
Christopher Morgan , Intel Corporation, Hillsboro, OR
Megan Knapp , Intel Corporation, Hillsboro, OR
Grace Mei Ee Khoo , Intel Corporation, Hillsboro, OR
Bathiya P. Senevirathna , Intel Corporation, Hillsboro, OR
Praneeth Ranga , Intel Corporation, Hillsboro, OR
Ryan Fredrickson , Intel Corporation, Hillsboro, OR
MIR Tanjidur Rahman , Intel Corporation, Hillsboro, OR
Travis Williams , Intel Corporation, Hillsboro, OR
Samantha Lubaba Noor , Intel Corporation, Hillsboro, OR
Manoj Devendhiran , Intel Corporation, Hillsboro, OR
Prasoon Joshi , Intel Corporation, Hillsboro, OR
Ashkan Abtahi , Intel Corporation, Hillsboro, OR
Kimberlee Celio , Intel Corporation, Hillsboro, OR
Joseph Basile , Intel Corporation, Hillsboro, OR
Eric Norum , Intel Corporation, Hillsboro, OR
Miriam Cezza , Intel Corporation, Hillsboro, OR
Matthew H. Kirsch , Intel Corporation, Hillsboro, OR
Samia N Rahman , Intel Corporation, Hillsboro, OR
Hasan Faraby , Intel Corporation, Hillsboro, OR
Joshua W. Kevek , Intel Corporation, Hillsboro, OR
Martin von Haartman , Intel Corporation, Hillsboro, OR
Baohua Niu , Intel Corporation, Hillsboro, OR

Summary:

Devices with backside power delivery and gate-all-around transistors constitute a massive challenge for probe-based fault isolation and device debug. We built a new fault isolation flow that leverages next-generation probe technologies and methods, advanced device prep techniques, and enhanced electrical diagnosis that is tailored for these new devices. The flow extends fault isolation to integrated circuits with backside power delivery and gate-all-around transistors, enabling process yield improvement in this new device manufacturing paradigm.