A Review of IO Debug Techniques in Chip-Level Failure Analysis: Case Studies and Workflow

Tuesday, November 18, 2025: 10:30 AM
3 (Pasadena Convention Center)
Mr. Thong Doan , NVIDIA, Santa Clara, CA

Summary:

Shrinking technology nodes and the adoption of advanced packaging have significantly increased the complexity of I/O debugging. Restricted physical access, signal integrity degradation, and limited fault isolation resolution collectively contribute to elusive failure signatures. This paper presents a multi-technique, non-destructive Electrical Failure Analysis (EFA) strategy to address complex I/O failures through real-world case studies. Techniques such as Photoemission Microscopy (PEM), Lock-in Thermography (LIT), and Static Laser Stimulation with Lock-In mode (LI-SLS) are evaluated in conjunction with circuit analysis and schematic/layout signal tracing. The results demonstrate that no single technique is sufficient; rather, an adaptive approach—built upon deep circuit understanding and close collaboration between design and physical failure analysis (PFA) teams—is essential for accurate fault localization and effective root cause analysis.