Backside Decapsulation of Small Outline Transistor (SOT) Packages Through Milling Techniques
Backside Decapsulation of Small Outline Transistor (SOT) Packages Through Milling Techniques
Thursday, November 20, 2025: 10:20 AM
2 (Pasadena Convention Center)
Summary:
Abstract— Decapsulation is a standard failure analysis process used to expose the active circuit of a die for visual inspection. Backside decapsulation offers easier fault localization by accessing the substrate layer, avoiding interference from topside metal lines. Common techniques include ferric chloride etching, mechanical peel-off, and backside polishing. However, these methods can be challenging for small packages like small outline transistor (SOT) devices, which have a down bond connecting the die to the die paddle — a connection critical for further analysis. This study applied the “Backside Preparation by Milling Approach of Module Device for Failure Analysis” [1] method on SOT packages. The technique effectively exposed the die’s backside while preserving the down bond and electrical functionality, verified through curve trace and bench testing (CT and BT) results.
Abstract— Decapsulation is a standard failure analysis process used to expose the active circuit of a die for visual inspection. Backside decapsulation offers easier fault localization by accessing the substrate layer, avoiding interference from topside metal lines. Common techniques include ferric chloride etching, mechanical peel-off, and backside polishing. However, these methods can be challenging for small packages like small outline transistor (SOT) devices, which have a down bond connecting the die to the die paddle — a connection critical for further analysis. This study applied the “Backside Preparation by Milling Approach of Module Device for Failure Analysis” [1] method on SOT packages. The technique effectively exposed the die’s backside while preserving the down bond and electrical functionality, verified through curve trace and bench testing (CT and BT) results.