Region-based Characterization of Defective Logic Circuits
Region-based Characterization of Defective Logic Circuits
Monday, November 17, 2025: 4:00 PM
3 (Pasadena Convention Center)
Summary:
Logic circuit diagnosis is a crucial step in failure analysis. A recently-proposed methodology called CHEF (CHaracterizing Elusive Logic Circuit Failures) leverages pseudo-exhaustive, physically-aware region testing to more precisely localize and characterize defects. Unlike traditional diagnosis methods that rely on fault models, which often fail to capture real-world defect behavior, CHEF exhaustively simulates all possible faulty subcircuits within a physical region and compares them against actual tester fail log data to ensure accurate diagnosis of timing-independent, combinational defects. CHEF then derives a custom logic model for the defect by comparing the faulty and fault-free Boolean functions. This work presents SPICY CHEF, which integrates transistor-level defect injection and SPICE simulation into the CHEF methodology. Using SPICE, it simulates the physical impact of defects injected into regions identified by CHEF, resulting in precise defect characteristics that match failure behavior. Unlike cell-aware diagnosis methods, SPICY CHEF handles both intra- and inter-cell defects and operates in a reverse, data-driven manner. Effectiveness is validated using a red-blue team methodology on designs like NVDLA and VexRiscv. Injected defects from the red team are compared to SPICY CHEF’s results, confirming its diagnostic accuracy and robustness in identifying hard-to-model defects.
Logic circuit diagnosis is a crucial step in failure analysis. A recently-proposed methodology called CHEF (CHaracterizing Elusive Logic Circuit Failures) leverages pseudo-exhaustive, physically-aware region testing to more precisely localize and characterize defects. Unlike traditional diagnosis methods that rely on fault models, which often fail to capture real-world defect behavior, CHEF exhaustively simulates all possible faulty subcircuits within a physical region and compares them against actual tester fail log data to ensure accurate diagnosis of timing-independent, combinational defects. CHEF then derives a custom logic model for the defect by comparing the faulty and fault-free Boolean functions. This work presents SPICY CHEF, which integrates transistor-level defect injection and SPICE simulation into the CHEF methodology. Using SPICE, it simulates the physical impact of defects injected into regions identified by CHEF, resulting in precise defect characteristics that match failure behavior. Unlike cell-aware diagnosis methods, SPICY CHEF handles both intra- and inter-cell defects and operates in a reverse, data-driven manner. Effectiveness is validated using a red-blue team methodology on designs like NVDLA and VexRiscv. Injected defects from the red team are compared to SPICY CHEF’s results, confirming its diagnostic accuracy and robustness in identifying hard-to-model defects.