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22 Session 22: Circuit Edit: Processing Strategies

Thursday, November 15, 2012: 12:55 PM-2:10 PM
102AB (Phoenix Convention Center)
Session Chairs:
Mr. Dane Scott and Mr. Michael DiBattista
12:55 PM
22.1
Preparation of Wafer Level Packaged Integrated Circuits using Pulsed Laser Assisted Chemical Etching
Dr. Robert D. Chivas, Varioscale, Inc; Dr. Niru Dandekar, Varioscale, Inc; Scott Silverman, Varioscale, Inc; Mr. Michael DiBattista, Qualcomm, Inc; Roddy Cruz, Qualcomm, Inc
1:20 PM
22.2
Multi-Site Full Thickness Backside Focused Ion Beam (FIB) Editing for eDRAM Array Address Descramble Verification
Mr. Steven B. Herschbein, IBM Systems & Technology; Mr. Carmelo F. Scrudato, IBM Systems & Technology; Mr. George K. Worth, IBM Systems & Technology; Mr. Edward S. Hermann, IBM Systems & Technology
1:45 PM
22.3
VIS-NIR LED Illumination in Backside Circuit Edit and Optical Probing Applications
Dr. Shida Tan, Intel Corporation; Mr. Richard Livengood, Intel Corporation; Mr. Dane Scott, Intel Corporation; Roy Hallstein, Intel Corporation; Patrick Pardy, Intel Corporation; Mr. John Giacobbe, Intel Corporation
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