Product Yield, Test & Diagnostics - POSTER

Wednesday, October 31, 2018: 2:20 PM-4:20 PM
Mr. Amit M. Jakati, GLOBALFOUNDRIES and Mr. Jayant DSouza, Mentor Graphics
Reproducing the fail from a production Memory ATE on a logic FA tester
Mr. Nivesh Rai, NXP Semiconductors
FA of SRAM DQ failure using BIST pattern
Mr. Keonil Kim, Samsung Electroncs Foundry business division
Improved Burn-in Stress Methodology for Stress Uniformity
Mr. Jungsuk Ko, Samsung Electronics; Mr. Hoonchang yang, Samsung Electronics; Mr. Hyungchae Jeon, Samsung Electronics; Mr. Gyuyoung Nam, Samsung Electronics; Mr. Youngseok Ryu, Samsung Electronics; Mr. Changyu Park, Samsung Electronics; Mr. Hongsun Hwang, Samsung Electronics; Dr. Taeyoung Oh, Samsung Electronics; Mr. Jonghoon Kim, Samsung Electronics; Mr. Seongjin Jang, Samsung Electronics
Successfully Look Up Table Distribution RAM (LUTRAM) Control Circuitry Fault Isolation with Different Test Methodologies and Conflict Results Analysis by Using Virtual IO (VIO) and Integrated Logic Analyzer (ILA) Debug Tools
Mr. Jingyao Huang, Xilinx Asia Pacific; Mrs. Jing Yang, Xilinx Asia Pacific; Mr. Peter Floyd Salinas, Xilinx Asia Pacific
See more of: Technical Program
<< Previous Session | Next Session >>