Package and Physical Analysis Challenges

Sunday, November 10, 2019: 8:00 AM-11:50 AM
D 137/138 (Oregon Convention Center)
Mr. Chris Richardson, Allied High Tech Products, Inc. and Mr. John Bescup, NASA JPL
8:00 AM
Chip Scale Packaging and Its Failure Analysis Challenges
Ms. Susan Li, Cypress Semiconductor
9:00 AM
Flip Chip and Backside Preparation Techniques
Dr. Edward I. Cole Jr., FASM, Sandia National Laboratories; Kira L. Fishgrab, Sandia National Laboratories; Dr. Daniel L. Barton, Sandia National Labs; Dr. Karoline Bernhard-Hofer, Infineon
10:00 AM
Morning Refreshment Break
10:20 AM
Advanced Package Level Fault Isolation
Dr. Lihong Cao, ASE US Inc
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