Dr. Nirakar Poudel

Senior Failure Analysis Enginner
NVIDIA
San Jose, CA
USA 95121

Papers:

Novel looping methodology for Laser Voltage Probing of stuck-at and at-speed fails in SSN architecture
CAD Alignment Methodologies for Accurate and Reliable Optical Fault Isolation at Sub-5nm Process Technologies
Investigating Decap LVP for On-Die Dynamic Voltage Droop Measurement