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| Poster |
| Location: Worcester Art Museum (Worcester Art Museum) |
| (Please check final room assignments on-site). |
Session Description: Poster topics this year involve the topics of optical techniques, TDR applications, delayering and sample preparation, analysis of new technologies, and various assorted analysis methods that don't fit into any of the standard session categories. Solicited poster categories include late-breaking news, and local (Boston area) university and company participation.
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| Editors: | Mr. Ted Kolasa Motorola SPS, Tempe, AZ
James Cargo Agere Systems, Allentown, PA
Mr. Stanley Swieck Analog Devices, Wilmington, MA
Mr. Michael Eskenazi Qualcomm Corporation, San Diego, CA
Felix Beaudoin IBM
Mr. Ted Hasegawa National Semiconductor, Santa Clara, CA
Mr. David Vallett IBM Systems and Technology Group, Essex Jct., VT |
| Session Chair: | Mr. Ted Kolasa Motorola SPS, Tempe, AZ |
| Optical Techniques | |
| P1 | | New Developments in IR Lock-in Thermography
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| P2 | | The root of all "IVA" - a quantitative analysis of LSIM bias/detection systems
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| P3 | | Correlation of Flash Memory Defects Detected with Passive and Active Localization Techniques
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| P4 | | Failure Analysis of SOI Bipolar device using Photon Emission Microscopy
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| P5 | | DEI Analysis of an OTP EPROM: Dynamic Electroluminescence Imaging (DEI) applied to an OTP EPROM memory device
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| TDR Applications | |
| P7 | | Failure analysis of broken stitch bonds in TSSOP packages using Scanning Acoustic Microscopy (SAM) and Time Domain Reflectometry (TDR)
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| Delayering and Sample Preparation | |
| P8 | | Multi Layer Automatic Front Side Delayering Techniques
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| P9 | | Advanced Mounting System and Method: To Establish and Maintain Predictable and Accurate Grind Plane Reference for Solder Joint Cross-Section Processing
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| P10 | | Chemical Delidding and Thin-Die Extraction of Flip-Chip Devices Using N-Methyl-2-Pyrrolidone
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| P11 | | DuPont EKC265TM PERR as a Copper Metallization Etchant for the Physical Deprocessing of Failing 0.12um Technology Devices
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| P12 | | Sample Preparation and Preservation for TEM Analysis of Copper Interconnect Integrated Circuit
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| Analysis of New Technologies | |
| P13 | | Red Phosphorous Induced Shorts in Plastic Packages
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| P14 | | Failure Modes, Reliability Analysis and Case Studies on Integration of Copper and Low k Technology
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| P15 | | Via Electromigration Related Functional Failure -a Case Study
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| Miscellaneous Analysis Techniques | |
| 9.2 | | Optimised Probing Flow for High Speed Fault Localization
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| P16 | | High Aspect Ratio Via Milling Endpoint Phenomena in Focused Ion Beam Modification of Integrated Circuits
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| P17 | | ESD Damage Simulation on RF MMIC Device
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| P18 | | Infra-Red Reflectance Microscopy for Daisy Chain Flip-Chip Device Failure Analysis
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| SPM | |
| P19 | | SCM Application in Semiconductor Failure Analysis and possible solution for the well inspection of advanced nanometer process
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| P20 | | Front-end Failure Analysis of Integrated Circuits Using Scanning Capacitance Microscopy
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